Better to know some
... than all
Encoder and Decoder
*The address decoder has a binary number with M bits as its input.
*It has 2M outputs.
*At any time, only 1 output line is ``on'' and all others are off.
*The line that is ``on'' specifies the desired column or row.
*For M=2, the decoder is shown in the diagram below.
*Notice how the binary representation of the input determines the selected output line.
Performs the inverse of the decoder, having 2n inputs and n outputs. However, a strict analogy with the decoder requires that only a single one of the 2n inputs be active at a time. Since the encoder cannot control its inputs to have a single input one, encoders nearly always occur as priority encoders. The following diagrams contrast parallel and iterative encoders. The primary difference being the iterative is inherently slower due to the longer propagation through the longer series of devices. Note that input x3 has the highest priority, and disables all lower priority inputs when it is active or z3=x3=1.