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RS and Flip-Flops
The RS flip-flop (RSFF) is the result of cross-connecting two NOR gates as shown in figure. The RS inputs are referred to as active ones.
Figure: The RS flip-flop constructed from NOR gates, and its circuit symbol and truth table. The ideal flip-flop has only two rest states, set and reset, defined by QQ'= 10 and QQ'= 01 , respectively. A very similar flip-flop can be constructed using two NAND gates as shown in figure. The R'S' inputs are now active zeros.
Figure: The R'S' flip-flop constructed from NAND gates, and its circuit symbol and truth table. These FFs are often referred to as the set/reset type and are un-clocked.
Clocked RS Flip-Flop
We first consider the static clocked (level-sensitive) RS flip-flop shown in figure. The symbol x in the following tables represents either the binary state 0 or 1.
Figure: The clocked RS flip-flop can be constructed from an RS flip-flop and two additional gates, the schematic symbol for the static clocked RSFF and its truth table.
The first five lines in the truth table give the static input and output states. The last four lines show the state of the outputs after a complete clock pulse p.
Master/Slave or Pulse Triggering
We can simulate a dynamic clock input by putting two flip-flops in tandem, one driving the other in a master/slave arrangement as shown in figure. The slave is clocked in a complementary fashion to the master.
Figure: An implementation of the master/slave flip-flop. This arrangement is still pulse triggered. The data inputs are written onto the master flip-flop while the clock is true and transferred to the slave when the clock becomes false. The arrangement guarantees that the QQ' outputs of the slave can never be connected to the slave's own RS inputs. The design overcomes signal racing (ie. the input signals never catch up with the signals already in the flip-flop). There are however a few special states when a transition can occur in the master and be transferred to the slave when the clock is high. These are known as ones catching and are common in master/slave designs.
The Edge-Triggered RS Flip-Flop
To adjust the clocked RS latch for edge triggering, we must actually combine two identical clocked latch circuits, but have them operate on opposite halves of the clock signal. The resulting circuit is commonly called a flip-flop, because its output can first flip one way and then flop back the other way. The clocked RS latch is also sometimes called a flip-flop, although it is more properly referred to as a latch circuit.
The two-section flip-flop is also known as a master-slave flip-flop, because the input latch operates as the master section, while the output section is slaved to the master during half of each clock cycle.
The edge-triggered RS NAND flip is shown below:
The edge-triggered RS flip-flop actually consists of two identical RS latch circuits, as shown above. However, the inverter connected between the two CLK inputs ensures that the two sections will be enabled during opposite half-cycles of the clock signal. This is the key to the operation of this circuit.
If we start with the CLK input at logic 0 as initially depicted above, the S and R inputs are disconnected from the input (master) latch. Therefore, any changes in the input signals cannot affect the state of the final outputs.
When the CLK signal goes to logic 1, the S and R inputs are able to control the state of the input latch, just as with the single RS latch circuit you already examined. However, at the same time the inverted CLK signal applied to the output (slave) latch prevents the state of the input latch from having any effect here. Therefore, any changes in the R and S input signals are tracked by the input latch while CLK is at logic 1, but are not reflected at the Q and Q' outputs.
When CLK falls again to logic 0, the S and R inputs are again isolated from the input latch. At the same time, the inverted CLK signal now allows the current state of the input latch to reach the output latch. Therefore, the Q and Q' outputs can only change state when the CLK signal falls from a logic 1 to logic 0. This is known as the falling edge of the CLK signal; hence the designation edge-triggered flip-flop.
By going to a master-slave structure and making the flip-flop edge-triggered, we have made sure that we can precisely control the moment when all flip-flops will change state. We have also allowed plenty of time for the master latch to respond to the input signals, and for those input signals to change and settle following the previous change of state.
There is still one problem left to solve: the possible race condition which may occur if both the S and R inputs are at logic 1 when CLK falls from logic 1 to logic 0. In the example above, we automatically assume that the race will always end with the master latch in the logic 1 state, but this will not be certain with real components. Therefore, we need to have a way to prevent race conditions from occurring at all. That way we won't have to figure out which gate in the circuit won the race on this particular occasion.
The solution is to add some additional feedback from the slave latch to the master latch. The resulting circuit is called a JK flip-flop.